The use of single and dual-damascene copper interconnect structures in semiconductor device manufacturing has received a great deal of attention due to the decreased resistivity of copper interconnects in comparison to aluminum interconnects. In typical single and dual-damascene copper interconnect structures, a tantalum (Ta) or tantalum-nitride (TaN) copper interconnect barrier layer is employed to prevent the undesirable diffusion of copper into, for example, a dielectric layer. A conventional copper interconnect structure formation process includes first depositing a tantalum or tantalum-nitride copper interconnect barrier layer on a substrate (e.g., a single or dual-damascene dielectric substrate) using Physical Vapor Deposition (PVD), followed by the deposition of a copper seed layer. A bulk copper layer is subsequently formed on the copper seed layer by electroplating.
In the field of semiconductor device manufacturing, deposition processes can be characterized by sidewall step coverage and aspect ratio. Sidewall step coverage is defined as the ratio of a layer""s thickness on the sidewall of a feature to that on a horizontal surface adjacent to the feature and is generally expressed as a percentage. Aspect ratio is defined as the height of a feature (e.g., a via or trench) versus the width of the feature. A drawback of the conventional copper interconnect process described above is the low sidewall step coverage obtained for Ta and TaN copper interconnect barrier layers formed using PVD techniques. For high aspect ratio via and trench features (e.g., aspect ratios of 4:1 and greater), the sidewall step coverage obtained with PVD techniques is typically around 10%. Tungsten-nitride (WXN) layers deposited using Chemical Vapor Deposition (CVD) have been investigated as potential copper interconnect barrier layers. WXN layers deposited by CVD, however, can also suffer from undesirably low sidewall step coverage, as well as from poor adhesion to underlying dielectric layers.
Still needed in the field, therefore, is a method for forming a copper interconnect barrier layer with a high sidewall step coverage (i.e., a sidewall step coverage of greater than 30% to conformal) and ample adhesion to an underlying dielectric layer. Also needed is a copper interconnect barrier structure that includes a copper interconnect barrier layer with a high sidewall step coverage.
The present invention provides a method for forming a tungsten-containing copper interconnect barrier layer (e.g., a tungsten [W] or tungsten-nitride [WXN] copper interconnect barrier layer) on a substrate with a high (e.g., greater than 30%) sidewall step coverage. The method also results in ample adhesion of the tungsten-containing copper interconnect barrier layer to any underlying dielectric layers.
A process according to one exemplary embodiment of the present invention includes first depositing, on a substrate, a thin titanium-nitride (TiN) or tantalum nitride (TaN) nucleation layer, followed by the formation of a tungsten-containing copper interconnect barrier layer (e.g., a W or WXN copper interconnect barrier layer) thereon. The tungsten-containing copper interconnect barrier layer can be formed, for example, using a CVD technique that employs a fluorine-free tungsten-containing gas (e.g., tungsten hexacarbonyl W[CO]6). Alternatively, the tungsten-containing copper interconnect barrier layer can be formed using a WF6-based Atomic Layer Deposition (ALD) technique.
The presence of a thin TiN (or TaN) nucleation layer on the substrate facilitates formation of a tungsten-containing copper interconnect barrier layer with a sidewall step coverage of greater than 30%. In addition, for the circumstance of a dielectric substrate (e.g., a single or dual-damascene copper interconnect substrate), the presence of the thin TiN nucleation layer on the dielectric substrate enables ample adhesion of the tungsten-containing copper interconnect barrier layer to the dielectric substrate.
Exemplary embodiments of a copper interconnect barrier layer structure according to the present invention includes either a thin titanium-nitride (TiN) nucleation layer or a thin tantalum-nitride (TaN) nucleation layer disposed directly on a dielectric structure (e.g., a single or dual-damascene copper interconnect dielectric structure). The copper interconnect barrier layer structure also includes a tungsten-containing copper interconnect barrier layer (e.g., a W or WXN copper interconnect barrier layer) formed on the thin TiN (or TaN) nucleation layer using, for example, a CVD technique that employs a fluorine-free tungsten-containing gas (e.g., tungsten hexacarbonyl (W[CO]6) or a WF6-based ALD technique.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description that sets forth illustrative embodiments, in which the principles of the invention are utilized, and the accompanying drawings (in which like numerals are used to designate like elements).